Jitter Attenuation, Multiplying PLL
  • ACS8944
    • Jitter Attenuating, Multiplying Phase Locked Loop for OC-12/STM-4
  • ACS8946
    • Jitter Attenuating, Multiplying Phase Locked Loop, with Protection Switch, for OC-12/STM-4 and GbE
  • SC561
    • Dual Output Low Noise LDO Linear Regulator
  • SC810
    • Single Input/Single Mode Single-cell Li-ion Battery Charger
  • SCDAS4F
    • Standard Recovery, High Current Center Tap and Doubler Rectifier Assemblies
Semtech ACS8944

Semtech ACS8944

Jitter Attenuating, Multiplying Phase Locked Loop for OC-12/STM-4

Not Recommended For New Designs, Consult Factory

The ACS8944 JAM PLL is a Jitter- Attenuating, Multiplying Phase-Locked Loop, for generating low jitter output clocks compliant up to SONET OC-12 and STM-4 622.08 MHz specifications.

Features


  • Meets rms jitter requirements of:
    • Telcordia GR-253-CORE for OC-3 and OC-12
    • ITU-T G.813/G.812 for STM-1 and STM-4 rates
    • ETSI EN300-462-7/EN302-084 up to STM-16 rates
  • Typical jitter generation down to:
    • 0.3 ps rms for 250 kHz to 5 MHz band for G.813, or EN300-462, at STM-4 (OC-12) rates
    • 2.8 ps rms for 12 kHz to 20 MHz band (against 4.02 ps rms for GR-253-CORE at OC-48 rate)
  • Pull-in range ±400 ppm about center input frequency
  • Frequency translation e.g. 19.44 MHz to 155.52 MHz
  • 3.3 V operation, - 40 to +85°C temperature range
  • Small outline leadless 7 mm x 7 mm QFN48 package
  • Demonstration Board available on request
  • PLL bandwidth and jitter peaking are fully adjustable.
  • Supports bandwidths from 2 kHz for superior input jitter filtering
  • Lead (Pb)-free version available (ACS8944T), RoHS and WEEE compliant

Applications


Packaging

QFN48

Order Codes

  • ACS8944T: Lead (Pb)-free packaged version of ACS8944; RoHS and WEEE compliant