Datasheet

Features

• Quad AC-Coupled CML Line-Side Output Ports
  • 25.0 to 28.3 Gbps per channel
  • 0.3 to 0.6 Volt pp SE/ 0.6 to 1.2Volt pp Differential Output Level, Typical (adjustable for reduced power)
  • 11 psec (typical) Rise/Fall Times
  • 3.7 psec p-p total jitter (typical)
  • Optional Line-side preskew function for MLD/CAUI application
  • Optional Line-side pre-emphasis to compensate loss due to PCB interconnect
• High-Speed Differential Clock Outputs with Highly Stable Clock-Data Skew and Low Phase Noise
  • Full (25 - 28.3 GHz) and Half-Rate (12.5 - 14.15 GHz) CML Clocks
  • Skew control of +/- 0.5UI (Note: 1UI = 1/f_Baud) for HSCLK[1:0] Output Pairs
  • 0.8 Volt pp Differential Output Level
• Reference Clock Clean-Up Loop Circuitry
• CAUI/MLD-compatible client-side interface
  • Optional SFI-S Compliant Deskew Function
  • Hot-plug compatible for ac-coupled inputs
  • Capable of dc-coupled operation with 1.2V source termination voltages
  • Independent enable/disable function controls each client-side input lane
• Optional input reference clock rate at 1/16th client-side baud rate (625.0 to 707.5 MHz) or 1/64th client-side baud rate (156.25MHz to 176.875MHz)
• On-Chip PRWS Error Checker and Pattern Generator: 27- ¹, 29 - ¹, 2¹¹ - 1, 2¹⁵ - 1, 2²³ - 1, or 2³¹-1 industry-standard patterns
  • On-chip bit and error counters for measuring BER
  • Parallel and lane-by-lane error checking capacities
  • Programmable 80-bit arbitrary pattern generator
• SPI Control Interface
• Temperature Sense Output Voltage
• Power Supply Voltages: +1.2 or +1.5V and -2.8V
• Package: Full BGA-style package

Applications

Packaging

Order Codes

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